Tokyo University, Taiwan Firms Craft 512-Core Chip

SHANGHAI — Dual core? That's so old school at the University of Tokyo, which recently finished up work on a 512 core chip in collaboration with Taiwan Semiconductor Manufacturing Co. and Alchip Technologies, a fabless ASIC company also from Taiwan.

The chip, called Sing, is part of the larger Grape DR project to create the next-generation of supercomputers, capable of 2,000 trillion transactions per second (2PFLOPS). The chip itself is designed as a math co-processor capable of 512 billion floating point operations per second running at a cool 500MHz. Its divide and conquer architecture keeps power down to about 60 watts.

With system-on-chip being an industry buzzword, this is surely among one of the ultimate SoC design challenges. Alchip engineers crafted 60 million logic gates and 10 million bits of SRAM, then handed it off to TSMC for a run on its 90-nanometer, eight-layer metal process. They claim the result was a first-pass silicon success.

The co-processors will be jammed together in clusters that will be mounted on PCI Express cards. They will then be slotted into servers that will themselves become powerful computing clusters.

According to the University of Tokyo, a Grape-DR system is comprised of clusters in far-flung places linked by high-speed Internet with IPv4/IPv6 dual stacks with bandwidth of 40Gbps to 400Gbps. An individual cluster is made up of 32 to 128 PCs with a Grape-DR card that has eight chips. Each clustered system has 50 terabytes to 400 terabytes of storage.

The end game is to create a supercomputer that can handily chew through math-intensive tasks, such as astrophysical particle simulation and genome sequencing analysis. It can also be used to explore the galaxy, in simulations that is.