Advanced Micro Devices on Thursday introduced code-reducing technology that is planned for the company's next-generation microprocessor expected in 2009.
SSE5 is AMD's new extension of the x86 instruction set. The specification is meant to maximize the efficiency of applications running on the platform by reducing the number of instructions needed to achieve a particular result.
SSE, introduced in 1999, stands for streaming SIMD extension. SIMD, or single instruction multiple data, is the instruction set for the x86 architecture. The latest technology is designed to boost software performance through the use of special instructions that can operate on multiple pieces of data at one time. SSE is as important to software performance as are multicore processor technology and the integration of specialized co-processors, AMD said.
SSE5 increases the number of inputs, or operands, an x86 instruction can handle from two to three. Such a capability is currently possible only on certain RISC architectures, AMD said. In addition, the specification introduces "fused multiply accumulate," an instruction that combines multiplication and addition to enable iterative calculations with one instruction. The simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, execution of complex vector mathematics, and other computing-intensive chores.
AMD has made SSE5 available to developers through its Web site. AMD plans to implement the specification in its next-generation processor core, code-named Bulldozer.
AMD often releases developer-related technology in advance of new chip platforms. In 2005, for example, the company released an early version of its virtualization technology, code-named Pacifica. More recently, AMD released the lightweight profiling proposal, which is a specification designed to help developers build software for multicore computing.